
DIPSwitchSettings
CompatibilitywithMIL‐STDcircuits
ThedriversandreceiversforV.11signalsarecompatiblewiththeMIL‐STDbalancedspecificationsandthe
V.10interfaceissimilartoMIL‐STDunbalanced.MIL‐STD‐100signalsusethesamenegativeMARKcondition
asTIAcircuits,sothereisnoneedtoinverttheTDandRDsignals.MIL
‐STD‐188‐114Aisset‐upforusercontrol
oftheMARKlevel,sotheneedfordatainversionattheFOMwillneedtobemadeonacase‐by‐casebasis.
IftheMIL‐STDinterfaceusesanyunbalancedsignals,suchasMIL‐STD‐188C(notethatthis
standardusesa
positiveMARK),thenprovisionswillneedtobemadetoexternallybiasonesideofthereceiversontheFOM
tousethemsingle‐ended.NotethattheMILstandardsareonlyanelectricalspecificationanddonotspecifya
pinoutorconnectortype,soacustom
cablewillberequiredinmanycases.
Asynchronous,Isochronous,orSynchronousoperation
TheFOMistransparenttodataandclockingformats,sotherearenoswitchsettingsfordistinguishingthe
differentmodesofoperation.WhenapairofFOM‐1090unitsisusedasmodemlinkbetweentwoDTEs,allof
theinputsignalsaretransferredtothecrossed‐overcorrespondingoutputs(i.e.
‐TTfromtheDTEisprovided
asRToutoftheFOM‐1090)attheoppositeend.WhentheFOMisusedinSendTimingapplications,certain
switchoptionsmaybeusedtoeliminateclockingissuesthatmayarise.Thoseoptionsareexplainedbelow.
SendDataRegenerationwhenusingSendTimingfromtheDCE
ThetypicalSendTimingset‐uphastheDCEsupplyingallclocks.TheSTsignalisgeneratedattheDCEandthen
carriedtotheremoteDTE.Inreturn,theremoteDTEthenclockstheSendDataoutofitselfontherisingedge
ofthesuppliedSTsignal.TheSend
DataiscarriedbacktotheDCEwhereitisclockedin,samplingthedatabit
onthefallingedgeofthegeneratedSTclock.Alignmentproblemsariseduetopropagationdelaywhencertain
combinationsofdatarateandcabledistance(bothcopperandfiber)resultintheSendData
transitions
occurringnearthefallingedgeoftheSTsignalattheDCE.
Asanexample,usingaroughnumberof4nsdelaypermeterofcable,25metersofcablewitha2.5mHzclock
willcausea180degreeshiftintheST‐SDrelationshipattheDCE
interface.(Thereisactually50metersof
propagationdelaysincetheclocktravels25metersinonedirectionandthedatatravels25metersinthe
other).ThisiswithouttakingintoaccountthedelaysofthelinedriversandreceiversintheDTE.
TheFOM‐1091regenerationoptionsmake
upforthisintwoways.ThefirstistocorrectforanySD‐ST
misalignmentduetopropagationdelayfromtheFOM‐1091totheDCEbydelayingtheSDsignaloutofthe
FOMbyonehalfofaSTclockcycle.ThesecondistheFOMhasthe
abilitytoretimetheincomingSDdata
internallywiththeincomingSTsignal,whichremovesanysamplingjitterfromtheSDsignalaswellas
correctingforpropagationdelays.
WhilethefallingedgeoftheSTsignalfromtheDCEisideallylocatedmid‐bitoftheSDsignalcoming
intothe
DCE,itisnotnecessaryforittobemid‐bit.Infact,it’susuallynotmid‐bitduetodelays.Thisisoften
misunderstood.Theactualrequirementisthattheset‐uptimefortheregisterthattheSDsignalisbeing
loadedintobemetandthis
isusuallyafractionoftheavailablebittime.Theonlytimethereisaproblemis
whenthefallingedgeoftheSTistooclosetotheSDtransitionsattheDCEinterfaceandthispreventstheset‐
uptimefrombeingmet.IftheSTfallingedge
isfarenoughawayfromtheSDtransitionedges(whenthenew
SDdatabithasmettheset‐uptime),theDCEwillstillclockthedatareliablyeventhoughitisn’tmid‐bit.Thisis
whymanySTtimingset‐upswillworkwithnoregenerationrequiredatall.
Whentheedgesaretoocloseat
theDCEtheFOMwillneedtoretimethedataontheoppositeedgeoftheSTsignalbysett ing switch 1.8to
ON.Thiswillallowthatwhenthepropagationdelaysaretakenintoaccounttheedgeshaveskewedenoughto
meet
theset‐uptimeattheDCE.
Notethatininstallationswherethe dataratemaybech angedorthecablelengthsmaychangeduetopatch
panelroutingofequipment,it’sentirelypossiblethatacombinationofswitchsettingsthatworksinone
scenariowillnotworkinanother.The
onlysolutiontothesesituationsistoinsertmoredelayinoneormore
oftheconfigurationsbyaddingtocablelengthuntilallofthescenarioswillworkwiththesameswitch
settings.
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